1. Field of the Invention
The present invention relates to a manufacturing method of a miniaturized structure of an element isolating film formed on the surface of a semiconductor substrate, a structure capable element isolating characteristics and the manufacturing method thereof.
The present invention relates to a structure capable of improving junction breakdown voltage in an isolating region in a field shield isolating structure and to the manufacturing method thereof.
2. Description of the Background Art
In a semiconductor integrated circuit, a variety of element isolating structures have been proposed for insulating and isolating a number of semiconductor elements formed on a silicon substrate.
Description will be given on an element isolating structure utilizing so called LOCOS (Local Oxidation of Silicon) isolating films.
FIG. 14 is a sectional view schematically showing a structure of a semiconductor device, e.g. a semiconductor storage device such as a memory in section. Referring to FIG. 14, on the surface of a p type silicon substrate formed are an element forming region L2 on which an MOS transistor 2 is formed and an element isolating region L1 on which a field oxide film 7 is formed. The MOS transistor 2 includes a gate electrode 3 formed on the surface of the p type silicon substrate 1 with a gate insulating film 4 therebetween. The top and the side of the gate electrode 3 is covered with an upper oxide film 18 and a sidewall oxide film 17. A pair of source/drain regions 5a, 5b are formed on the surface of the silicon substrate 1. The source/drain regions have a so-called LDD (Lightly Doped Drain) structure formed of the n.sup.+ impurity region 5a of high concentration and the n.sup.- impurity region 5b of low concentration.
The field oxide film 7 formed in the element isolating region has a large thickness. The field oxide film 7 is formed by the LOCOS method. A channel stop layer 8 formed of a p.sup.+ impurity region having a concentration higher than that of the substrate 1 is formed under the field oxide film 7. The channel stop layer 8 is provided to improve element isolating ability by preventing an inversion layer from being formed in the region by means of increasing the concentration of the substrate in the underlying region of the field oxide film 7.
FIG. 14 shows an electrode layer 6 which extends over the upper portion of, for example, the field oxide film 7.
Now, description will be given on the manufacturing method of the semiconductor device shown in FIG. 14 by referring to FIGS. 15A-15G.
Referring to FIG. 15A, an underlying oxide film 14, a nitride film 9 and a resist 10 are sequentially formed on the p type silicon substrate 1. A prescribed form of opening is formed by patterning the resist 10 and the nitride film 9 using a lithography method and an etching method.
Now, referring to FIG. 15B, p type impurity ions 12 such as boron are implanted onto the surface of the silicon substrate 1, using the patterned resist 10 and the nitride film 9 as masks.
Referring to FIG. 15C, the field oxide film 7 having a thickness of thousands of .ANG. is formed by vapor oxidation of the silicon substrate 1. At the time, the boron ions 12 are diffused in the substrate, thereby forming the channel stop layer 8.
Referring to FIG. 15D, the nitride film 9 and the underlying oxide film 14 are removed. A gate oxide film 4 having a thickness of tens of .ANG. is formed again on the surface of the silicon substrate 1 by performing thermal oxidation. By utilizing a CVD (Chemical Vapor Deposition) method, a polysilicon layer 3 having a thickness of thousands of .ANG. is formed on the surface thereof, on the surface of which an oxide film 18 is formed.
Referring to FIG. 15E, upon applying the resist 10 on the surface of the oxide film 18, patterning is carried out thereon, and the oxide film 18 and the polysilicon layer 3 are patterned into a prescribed form using the patterned resist 10 as a mask, thereby forming the gate electrode 3 or the electrode layer 6.
Now, referring to FIG. 15F, a first amount of n type impurity ions 19 is implanted into the silicon substrate 1 utilizing the gate electrode 3, etc. as a mask, so that an n.sup.- impurity region 5b of low concentration is formed.
Referring to FIG. 15G, sidewall oxide films 17 are formed on the sidewalls of the gate electrode 3 and then a highly concentrated n.sup.+ impurity region 5a is formed by implanting a second amount of n type impurity ions 20 onto the surface of the silicon substrate 1, using the sidewall oxide films 17 as masks. The semiconductor device shown in FIG. 14 is manufactured by the above described process.
There exist, however, the following problems in a conventional element isolating structure as described above.
So called bird's beaks are formed on the opposing ends of the field oxide film 7 formed by the conventional LOCOS method. In other words, the formation of a bird's beak region in FIG. 14 increases the width of the element isolating region L.sub.1 and reduces the area of the element forming region L.sub.2, thereby preventing high density integration of the element structure.
Another problem concerned is that a junction region is formed in which the highly concentrated channel stop layer 8 formed under the field oxide film 7 is in a direct contact with the highly concentrated n.sup.+ impurity region 5a of the MOS transistor 2 and, therefore, it was difficult to keep the junction breakdown voltage of the region at a high level.
Now, description will be given on another example of an element isolating structure in a semiconductor integrated circuit which employs a field shield method using a high resistance at the time of a reverse bias in a pn junction. FIG. 16 is a sectional view of an isolating structure of an MOS transistor produced in accordance with a conventional field shield method. In the figure, two MOS transistors 2, 2 adjacent to each other are insulated and isolated by a field shield isolation 10. The MOS transistor 2 includes a gate electrode 4 formed on the surface of a p type silicon substrate 1 with a gate insulating film 3 therebetween, and a pair of source/drain regions 5, 5 formed in the surface of the p type silicon substrate having a prescribed space therebetween. The upper surface and the side surface of the gate electrode 4 are each covered with an upper insulating layer 6a and side insulating layers 6b, respectively. The field shield isolation 10 includes a field shield electrode layer 12 formed on the surface region of the p type silicon substrate 1 between each of source/drain regions 5, 5 of the adjacent MOS transistors 2, 2 having a shield gate insulating layer 11 therebetween. The field shield electrode layer 12 is formed surrounding the region on which the MOS transistor 2 is formed. The upper surface and the side surface of the field shield gate electrode 12 are covered with an upper insulating layer 13a and side insulating layers 13b, respectively.
Now, description will be given on the operation of the field shield isolation 10. FIG. 17 is a view showing the operation of a conventional field shield isolation. The field shield isolation 10 constitutes a transistor structure by the n.sup.+ source/drain regions 5, 5 of the MOS transistor disposed adjacent to each other, the shield gate insulating layer 11 and the field shield electrode layer 12. A negative voltage is applied to the field shield gate electrode 12 so that the transistor is reversely biased, and holes are induced beneath the shield gate insulating layer 11, thereby changing the type of the surface region of the p type silicon substrate 1 between the two n.sup.+ source/drain regions 5, 5 from p type to p.sup.+ type to form a p.sup.+ region 16. An n.sup.30 p.sup.30 n.sup.+ structure is therefore formed between the adjacent MOS transistors, thereby performing insulation and isolation between the two MOS transistors.
In the above described field shield isolation structure, a silicon oxide film having a thickness of thousands of .ANG. in the isolating region is formed, and the entire device is advantageously flattened, when compared to a so-called LOCOS (Local Oxidation of Silicon) method in which development of an n type inversion layer on the surface of a substrate is prevented by increasing the threshold voltage of an isolating portion.
Now, description will be given on the manufacturing method of a semiconductor device having the field shield isolation shown in FIG. 16. FIGS. 18A-18E are sectional views showing the manufacturing process of the semiconductor device shown in FIG. 16.
As shown in FIG. 18A, the surface of a p type semiconductor substrate is thermally oxidized, thereby forming a silicon oxide film 22 having a thickness of some tens of .ANG.. Further, a polysilicon layer 23 having a thickness of some thousands of .ANG. and an oxide film 24 having a thickness of some thousands .ANG. of are sequentially deposited on the surface of the silicon oxide film 22 by a CVD method (Chemical Vapor Deposition) Resists 21 are applied onto the surface of the oxide film 24 and patterning into a prescribed form is performed thereon, using a lithography method or an etching method.
Subsequently, as shown in FIG. 18B, using the patterned resists 21 as masks the oxide film 24, the polysilicon layer 23 and the thermal oxide film 22 are sequentially patterned to form the gate insulating film 3, the gate electrode 4, the upper insulating layer 6a of the MOS transistor as well as the shield gate insulating layer 11, the field shield electrode layer 12 and the upper insulating layer 13a of the field shield isolating structure.
Furthermore, as shown in FIG. 18C, an oxide film 29 oxidized at a high temperature having a thickness of some thousands of .ANG. is deposited on the surface of the p type silicon substrate 1, after the resists 21 being removed.
As shown in FIG. 18D, the high temperature oxide film 29 is anisotropically and selectively etched to be removed, and then sidewall insulating layers 6b and, 13b are formed on the sidewalls of the gate electrode 4 and the field shield electrode layer 12, respectively.
Subsequently, as shown in FIG. 18E, phosphoric ions 30 are implanted onto the surface of the p type silicon substrate, using as masks the gate electrode 4 and the field shield electrode layer 12 covered by the upper insulating layers 6a and 13a and the sidewall insulating layers 6b and 13b, respectively, thereby forming n.sup.+ source/drain regions 5, 5. The semiconductor device comprising the field shield isolating structure is manufactured in accordance with the above described process.
Referring back to FIG. 17, in the conventional field shield isolating structure, an n.sup.+ p.sup.+ junction is formed between the source/drain region 5 of the MOS transistor and the isolation region. In such a highly concentrated pn junction region, its junction breakdown voltage becomes low because its depletion layer has its extent restricted.
As a conventional technique related to the present invention, for example, a field shield isolating structure provided with a shield electrode having a shield gate insulating film thicker than the gate insulating film of an adjacent MOS transistor in order to increase the threshold voltage of the field shield isolating structure is disclosed in Japanese Patent Laying Open 62-244163, or a manufacturing method of an LDD structure by an oblique rotating ion implantation method is disclosed in Japanese Patent Laying Open 61-258475.